The present invention relates to electrically programmable read only memories (EPROM), and in particular to EPROMs employing both bipolar and complementary field effect transistors (BiCMOS).
Two popular circuit families are the transistor-to-transistor logic (TTL) and emitter coupled logic (ECL). CMOS circuits operate with TTL voltage levels, with high and low voltage levels of five and zero volts, respectively. Typically, a low level is defined as below 0.4 volts and a high level as above 2.4 volts, with a 5 volt voltage supply being used. This provides for a large voltage swing and thus large immunity to noise, but at the expense of slower speed due to the large transition needed. ECL circuits, on the other hand, are implemented with bipolar transistors, and operate with a voltage swing of approximately 0.8 volts, or the V.sub.BE of the bipolar transistor. Usually, a negative supply is used, with -4.5 or -5.2 volts being typical. Such circuits typically are used to drive a matched impedance output with a 50 ohm value. The 50 ohm value requires a large driving current and the matched impedance output eliminates reflections which may cause noise problems in a system having low noise margin.
Programmable read only memories (PROMs) have been developed using each technology. PROMs differ from Random Access Memories (RAMs) in their operation and structure. RAMs have both data inputs, data outputs and address inputs for selecting the data locations. PROMs have only address inputs and data outputs because they are only read after programming. The data outputs function as data inputs during programming.
Examples of two bipolar PROM cells, each of which can be programmed only once, are shown in FIGS. 1 and 2. Bipolar erasable PROMs (EPROMs) have not been developed. FIG. 1 shows a metal fuse configuration in which a fuse 10 is coupled in series with a diode 12 between a word line 14 and a bit line 16. By providing a large current pulse to a fuse, the fuse is melted away, or blown, thus programming the connection. The open connection can be interpreted by suitable addressing and reading circuitry as a zero or one, with the closed connection interpreted complementarily.
A transistor fuse is shown in FIG. 2. There, a bipolar transistor 18 is coupled between word line 14 and bit line 16. A reverse current through the transistor programs it by shorting the emitter-base junction, causing the transistor to behave functionally as a diode. Importantly, the memory cells of both FIG. 1 and FIG. 2 can be programmed once only and cannot have the programming reversed. These memory cells have the advantage, however, being operable with ECL voltage levels, using a 0.8 volt swing.
Typically, test rows and test columns of memory cells are included for testing the speed of a bipolar PROM chip prior to shipment to a customer. The rest of the memory cell array will not be programmed until the customer receives the chip, and thus cannot be tested prior to customer shipment. Because the main part of the array cannot be programmed and tested prior to customer shipment, it cannot be determined whether it will perform at the same speed as the test rows and columns. Accordingly, a margin of error is built in so that the test rows and columns must be faster than the speed in the product specification by a certain amount. This allows a "guard band" in case some of the actual array rows and columns are slower. Because the entire array cannot be programmed and tested prior to shipment, there are a larger number of failures after programming in the field than for CMOS EPROMs, which can be fully tested before shipment.
Because fuses are used for ECL PROMs, a high current pulse is necessary to blow the fuse. This requires a large current driver which may be the same driver as is used for sensing, or may be a separate driver coupled to the same line. In either case, the large driver adds to the capacitance of the line, thus slowing performance. In addition, wider metal lines are required to handle the large current pulses. Since the cells are read using the same metal lines, the lines are larger than they need to be for the read operation. Typical ECL PROMs have an access time of 10-25 nanoseconds (ns).
FIG. 3A is a block diagram of one embodiment of a complete memory circuit for one row (word line) 21 and one column (bit line) 23 of an array 29 using the cell of FIGS. 1 or 2. For programming, a bit to be programmed has its output pin 32 selected. This causes a high current pulse to be sent through program select and programming circuit 31 on column line 23. Any cell selected by not having a high value applied to its word line (i.e., word line 21) will have its fuse blown and be programmed. Only the bits to be programmed have a voltage applied to their output pin 32. After programming, during a read operation, an input pin 20 receives an address signal and provides it through an ECL input buffer 22 to an ECL decode circuit 24 to select the proper memory cell from thousands of other memory cells on the same integrated circuit. Output signals are provided through an ECL sense circuit 28 to an ECL output buffer 30 and an output pin 32. Of course, the ECL decode and ECL sense circuits actually are coupled to multiple memory cells, with only one being shown for simplicity.
FIG. 3B shows several of the circuits of FIG. 3A and a portion of an array 29. As can be seen, each row line has input buffer 22 and an ECL decode circuit 24. Each bit line (column) has an ECL sense circuit 28, an ECL output buffer 30 and a program select and high current programming circuit 31. Array 29 contains thousands of memory cells 26, with only a few shown for simplicity.
As can be seen, during programming, not only must the proper word line be selected by decoding the address input, but the bit line corresponding to the bit to be programmed must be selected by providing inputs on the data output pins. Thereafter, during a read operation, only the input words need be decoded, with each providing a multiple bit output byte on the plurality of bit lines. It will be appreciated that the decoding circuit has been somewhat simplified for explanation. Although a separate input buffer is provided for each address bit, the outputs of these input buffers are coupled into a single decode circuit which selects one of a large number of output word lines in response to a limited number of address bit inputs. Similar decoding, using components which can handle high currents, must be provided in high current programming circuit 27. Subsequent figures also use a simplified block for the decode circuit.
In contrast to bipolar technology, erasable PROMs (EPROMs) have been developed using MOS technology. An MOS EPROM cell is shown in FIG. 4 with word line 14 coupled to bit line 16 by a MOS transistor 34. Transistor 34 includes a floating gate 35, electrically isolated from the control gate 37. The transistor is programmed by electrons flowing onto the floating gate and being trapped there. This causes the floating gate to act as a capacitor holding charge, thereby altering the functionality of the transistor in a detectable manner, e.g. changing its threshold voltage. In one type cell, the programming is done by bringing both the word and bit lines high.
The MOS memory cell of FIG. 4 operates at TTL voltage levels, but has the advantage of being erasable. It can be erased, for example, by removing the charge from the floating gate using ultraviolet light or electrical techniques. Thus, a circuit can be programmed and verified, then erased and reprogrammed if necessary. The capability of reprogramming eliminates the need for test cells as in bipolar PROM circuits. One advantage of the memory cell of FIG. 4 is that it can be programmed using the standard 12.5 volt CMOS programming level (and later read with standard 0-5 volt I/O levels) while the bipolar PROM cells shown in FIGS. 1 and 2 typically require large current pulses for programming.
A typical MOS EPROM circuit is shown in FIG. 5. As shown, the circuit uses an array 43 of the cells of FIG. 4 with an input pin 36, input buffer 38 and decode circuit 40 for each word line 41. Each memory cell 42 is also connected to a bit line 47, which is coupled to a sense circuit 44, output buffer 46 and output pin 48. To program a memory cell 42 of FIG. 5, a 12.5 volt signal is provided on a Vpp pin 39 to address decode circuit 40 to the selected word line 41. Vpp pin 39 not only supplies the high voltage needed for programming, but also selects the programming mode when asserted by enabling programming circuit 45.
Any cell connected to a high word line and a bit line which is at a high value, such as bit line 47, will be programmed. An input provided through output pin 48 and programming circuit 45 causes bit line 47 to be a high value. Thus, this circuit requires a programming circuit coupled to the output pin, just as the bipolar PROM requires a programming circuit. However, the separate high current data input circuitry coupled to the output (or combined circuitry with high current capability) is eliminated. During a read operation, 5 volt levels are used to select the word line through input buffer 38 and decode circuit 40 with the bit lines being sensed through sense circuit 44 and output buffer 46.
Unfortunately, a typical access time for a CMOS EPROM is about 100-200 ns. Thus, there is a significant tradeoff between ECL and CMOS for programmable memories. The CMOS EPROMs give reprogrammability to the customer and the ability to program and test prior to customer shipment, but at the expense of a significantly greater access time. ECL PROMs, on the other hand, are faster, but cannot be fully tested prior to shipment and cannot be reprogrammed.